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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local elpida memory, inc. for availability and additional information. mos integrated circuit mc-458cb64esb , 458cb64psb 8m-word by 64-bit synchronous dynamic ram module (so dimm) document no. e0068n10 (1st edition) (previous no. m12263ejav0ds00) date published january 2001 cp (k) printed in japan data sheet elpida memory, inc. is a joint venture dram company of nec corporation and hitachi, ltd. description the mc-458cb64esb and mc-458cb64psb are 8,388,608 words by 64 bits synchronous dynamic ram module (small outline dimm) on which 4 pieces of 128m sdram: pd45128163 are assembled. these modules provide high density and large quantities of memory in a small space without utilizing the surface- mounting technology on the printed circuit board. decoupling capacitors are mounted on power supply line for noise reduction. features ? 8,388,608 words by 64 bits organization ? clock frequency and access time from clk part number /cas latency clock frequency access time from clk (max.) (min.) MC-458CB64ESB-A10B cl = 3 100 mhz 7 ns cl = 2 67 mhz 8 ns mc-458cb64psb-a10b cl = 3 100 mhz 7 ns cl = 2 67 mhz 8 ns ? fully synchronous dynamic ram, with all signals referenced to a positive clock edge ? pulsed interface ? possible to assert random column address in every cycle ? quad internal banks controlled by ba0 and ba1 (bank select) ? programmable burst-length (1, 2, 4, 8 and full page) ? programmable wrap sequence (sequential / interleave) ? programmable /cas latency (2, 3) ? automatic precharge and controlled precharge ? cbr (auto) refresh and self refresh ? single +3.3 v 0.3 v power supply ? lvttl compatible ? 4,096 refresh cycles/64 ms ? burst termination by burst stop command and precharge command ? 144-pin small outline dual in-line memory module (pin pitch = 0.8 mm) ? unbuffered type ? serial pd eol produc t
data sheet e0068n10 2 ordering information part number clock frequency mhz (max.) package mounted devices MC-458CB64ESB-A10B 100 mhz 144-pin small outline dimm (socket type) edge connector: gold plated 4 pieces of pd45128163g5 (rev. e) (10.16mm (400) tsop (ii)) mc-458cb64psb-a10b 100 mhz 25.4 mm height 4 pieces of pd45128163g5 (rev. p) (10.16mm (400) tsop (ii)) eol produc t
data sheet e0068n10 3 pin configuration 144-pin dual in-line memory module socket type (edge connector: gold plated) 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 vss dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 vss dqmb0 dqmb1 a0 a1 a2 vss dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 vss nc nc 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 clk0 vcc /ras /we /cs0 nc nc vss nc nc dq 16 dq 17 dq 18 dq 19 vss dq 20 dq 21 dq 22 dq 23 vcc a6 a8 vss a9 a10 vcc dqmb2 dqmb3 vss dq 24 dq 25 dq 26 dq 27 dq 28 dq 29 dq 30 dq 31 vss sda 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 vss dq 32 dq 33 dq 34 dq 35 vcc dq 36 dq 37 dq 38 dq 39 vss dqmb4 dqmb5 vcc a3 a4 a5 vss dq 40 dq 41 dq 42 dq 43 vcc dq 44 dq 45 dq 46 dq 47 vss nc nc 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 cke0 vcc /cas nc nc nc clk1 vss nc nc vcc dq 48 dq 49 dq 50 dq 51 vss dq 52 dq 53 dq 54 dq 55 vcc a7 ba0 (a13) vss ba1 (a12) a11 vcc dqmb6 dqmb7 vss dq 56 dq 57 dq 58 dq 59 vcc dq 60 dq 61 dq 62 dq 63 vss scl vcc cc v cc v cc v cc v cc v cc v /xxx indicates active low signal. a0 - a11 : address inputs [row: a0 - a11, column: a0 - a8] ba0(a13), ba1(a12) : sdram bank select dq0 - dq63 : data inputs/outputs clk0, clk1 : clock input cke0 : clock enable input /cs0 : chip select input /ras : row address strobe /cas : column address strobe /we : write enable dqmb0 - dqmb7 : dq mask enable sda : serial data i/o for pd scl : clock input for pd v cc : power supply v ss : ground nc : no connection eol produc t
data sheet e0068n10 4 block diagram /we /cs0 a0 - a11 a0 - a11 : d0 - d3 serial pd scl sda a0 a1 a2 dqmb0 dqmb1 /cs /we d0 ldqm udqm dq 0 dq 1 dq 4 dq 3 dq 2 dq 5 dq 6 dq 7 dqmb2 dqmb3 /cs /we d1 ldqm udqm dqmb6 dqmb7 /cs /we d3 ldqm udqm dqmb4 dqmb5 /cs /we d2 ldqm udqm dq 0 dq 1 dq 2 dq 5 dq 4 dq 3 dq 6 dq 7 dq 8 dq 9 dq 10 dq 13 dq 12 dq 11 dq 14 dq 15 dq 15 dq 14 dq 11 dq 12 dq 13 dq 10 dq 9 dq 8 dq 16 dq 17 dq 18 dq 21 dq 20 dq 19 dq 22 dq 23 dq 24 dq 25 dq 26 dq 29 dq 28 dq 27 dq 30 dq 31 dq 8 dq 9 dq 12 dq 11 dq 10 dq 13 dq 14 dq 15 dq 7 dq 6 dq 3 dq 4 dq 5 dq 2 dq 1 dq 0 dq 7 dq 6 dq 3 dq 4 dq 5 dq 2 dq 1 dq 0 dq 8 dq 9 dq 12 dq 11 dq 10 dq 13 dq 14 dq 15 dq 48 dq 49 dq 50 dq 53 dq 52 dq 51 dq 54 dq 55 dq 56 dq 57 dq 58 dq 61 dq 60 dq 59 dq 62 dq 63 dq 32 dq 33 dq 34 dq 37 dq 36 dq 35 dq 38 dq 39 dq 40 dq 41 dq 42 dq 45 dq 44 dq 43 dq 46 dq 47 dq 0 dq 1 dq 4 dq 3 dq 2 dq 5 dq 6 dq 7 dq 15 dq 14 dq 11 dq 12 dq 13 dq 10 dq 9 dq 8 /ras /ras : d0 - d3 /cas /cas : d0 - d3 cke0 cke : d0 - d3 ba0 a13 : d0 - d3 clk0 clk : d0, d2 clk : d1, d3 10 ? v cc d0 - d3 d0 - d3 v ss c ba1 a12 : d0 - d3 clk1 10pf remark d0 - d3: pd45128163 (2m words 16 bits 4 banks) eol produc t
data sheet e0068n10 5 electrical specifications ? all voltages are referenced to v ss (gnd). ? after power up, wait more than 100 s and then, execute power on sequence and cbr (auto) refresh before proper device operation is achieved. absolute maximum ratings parameter symbol condition rating unit voltage on power supply pin relative to gnd v cc C0.5 to +4.6 v voltage on input pin relative to gnd v t C0.5 to +4.6 v short circuit output current i o 50 ma power dissipation p d 4 w operating ambient temperature t a 0 to +70 c storage temperature t stg C55 to +125 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition min. typ. max. unit supply voltage v cc 3.0 3.3 3.6 v high level input voltage v ih 2.0 v cc + 0.3 v low level input voltage v il C0.3 + 0.8 v operating ambient temperature t a 0 70 c capacitance (t a = 25 c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c i1 a0 - a11, ba0 (a13), ba1 (a12), /ras, /cas, /we 30 pf c i2 clk0 30 c i3 cke0 30 c i4 /cs0 30 c i5 dqmb0 -dqmb7 10 data input/output capacitance c i/o dq0 - dq63 10 pf eol produc t
data sheet e0068n10 6 dc characteristics (recommended operating conditions unless otherwise noted) parameter symbol test condition min. max. unit notes operating current i cc1 burst length = 1, t rc t rc(min.) /cas latency = 2 440 ma 1 i o = 0 ma /cas latency = 3 440 precharge standby current i cc2 p cke v il(max.) , t ck = 15 ns 4 ma in power down mode i cc2 ps cke v il(max.) , t ck = 4 precharge standby current i cc2 n cke v ih(min.) , t ck = 15 ns, /cs v ih(min.) , 80 ma in non power down mode input signals are changed one time during 30 ns. i cc2 ns cke v ih(min.) , t ck = , input signals are stable. 32 active standby current in i cc3 p cke v il(max.) , t ck = 15 ns 20 ma power down mode i cc3 ps cke v il(max.) , t ck = 16 active standby current in i cc3 n cke v ih(min.) , t ck = 15 ns, /cs v ih(min.) , 120 ma non power down mode input signals are changed one time during 30 ns. i cc3 ns cke v ih(min.) , t ck = , input signals are stable. 80 operating current i cc4 t ck t ck(min.) , i o = 0 ma /cas latency = 2 400 ma 2 (burst mode) /cas latency = 3 560 cbr (auto) refresh current i cc5 t rc t rc(min.) /cas latency = 2 880 ma 3 /cas latency = 3 880 self refresh current i cc6 cke 0.2 v 8 ma input leakage current i i(l) v i = 0 to 3.6 v, all other pins not under test = 0 v C 4 + 4 a output leakage current i o(l) d out is disabled, v o = 0 to 3.6 v C 1.5 + 1.5 a high level output voltage v oh i o = C 4.0 ma 2.4 v low level output voltage v ol i o = + 4.0 ma 0.4 v notes 1. i cc1 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc1 is measured on condition that addresses are changed only one time during t ck(min.) . 2 . i cc4 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc4 is measured on condition that addresses are changed only one time during t ck(min.) . 3. i cc5 is measured on condition that addresses are changed only one time during t ck(min.) . eol produc t
data sheet e0068n10 7 ac characteristics (recommended operating conditions unless otherwise noted) test conditions parameter value unit ac high level input voltage / low level input voltage 2.4 / 0.4 v input timing measurement reference level 1.4 v transition time (input rise and fall time) 1 ns output timing measurement reference level 1.4 v t ck t ch t cl 2.4 v 1.4 v 0.4 v clk 2.4 v 1.4 v 0.4 v input t setup t hold output t ac t oh eol produc t
data sheet e0068n10 8 synchronous characteristics parameter symbol -a 10b unit note min. max. clock cycle time /cas latency = 3 t ck3 10 ns /cas latency = 2 t ck2 15 ns access time from clk /cas latency = 3 t ac3 7 ns 1 /cas latency = 2 t ac2 8 ns 1 clk high level width t ch 3.5 ns clk low level width t cl 3.5 ns data-out hold time t oh 3 ns 1 data-out low-impedance time t lz 0 ns data-out high-impedance time /cas latency = 3 t hz3 3 7 ns /cas latency = 2 t hz2 3 8 ns data-in setup time t ds 2.5 ns data-in hold time t dh 1 ns address setup time t as 2.5 ns address hold time t ah 1 ns cke setup time t cks 2.5 ns cke hold time t ckh 1 ns cke setup time (power down exit) t cksp 2.5 ns command (/cs0, /ras, /cas, /we, dqmb0 - dqmb7) setup time t cms 2.5 ns command (/cs0, /ras, /cas, /we, dqmb0 - dqmb7) hold time t cmh 1 ns note 1. output load output z = 50 ? 50 pf eol produc t
data sheet e0068n10 9 asynchronous characteristics parameter symbol -a 10b unit note min. max. ref to ref/act command period t rc 90 ns act to pre command period t ras 60 120,000 ns pre to act command period t rp 30 ns delay time act to read/write command t rcd 30 ns act(0) to act(1) command period t rrd 20 ns data-in to pre command period t dpl 10 ns data-in to act(ref) command /cas latency = 3 t dal3 1clk+30 ns period (auto precharge) /cas latency = 2 t dal2 1clk+30 ns mode register set cycle time t rsc 2 clk transition time t t 1 30 ns refresh time (4,096 refresh cycles) t ref 64 ms eol produc t
data sheet e0068n10 10 serial pd (1/2) byte no. function described hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notes 0 defines the number of bytes written into serial pd memory 80h 1 0 0 0 0 0 0 0 128 bytes 1 total number of bytes of serial pd memory 08h 0 0 0 0 1 0 0 0 256 bytes 2 fundamental memory type 04h 0 0 0 0 0 1 0 0 sdram 3 number of rows 0ch 0 0 0 0 1 1 0 0 12 rows 4 number of columns 09h 0 0 0 0 1 0 0 1 9 columns 5 number of banks 01h 0 0 0 0 0 0 0 1 1 bank 6 data width 40h 0 1 0 0 0 0 0 0 64 bits 7 data width (continued) 00h 0 0 0 0 0 0 0 0 0 8 voltage interface 01h 0 0 0 0 0 0 0 1 lvttl 9 cl = 3 cycle time -a10b a0h 1 0 1 0 0 0 0 0 10 ns 10 cl =3 access time -a10b 70h 0 1 1 1 0 0 0 0 7 ns 11 dimm configuration type 00h 0 0 0 0 0 0 0 0 non-parity 12 refresh rate/type 80h 1 0 0 0 0 0 0 0 normal 13 sdram width 10h 0 0 0 1 0 0 0 0 16 14 error checking sdram width 00h 0 0 0 0 0 0 0 0 none 15 minimum clock delay 01h 0 0 0 0 0 0 0 1 1 clock 16 burst length supported 8fh 1 0 0 0 1 1 1 1 1, 2, 4, 8, f 17 number of banks on each sdram 04h 0 0 0 0 0 1 0 0 4 banks 18 /cas latency supported 06h 0 0 0 0 0 1 1 0 2, 3 19 /cs latency supported 01h 0 0 0 0 0 0 0 1 0 20 /we latency supported 01h 0 0 0 0 0 0 0 1 0 21 sdram module attributes 00h 0 0 0 0 0 0 0 0 22 sdram device attributes: general 0eh 0 0 0 0 1 1 1 0 23 cl = 2 cycle time -a10b f0h 1 1 1 1 0 0 0 0 15 ns 24 cl = 2 access time -a10b 80h 1 0 0 0 0 0 0 0 8 ns 25-26 00h 0 0 0 0 0 0 0 0 27 t rp(min.) -a10b 1eh 0 0 0 1 1 1 1 0 30 ns 28 t rrd(min.) -a10b 14h 0 0 0 1 0 1 0 0 20 ns 29 t rcd(min.) -a10b 1eh 0 0 0 1 1 1 1 0 30 ns 30 t ras(min.) -a10b 3ch 0 0 1 1 1 1 0 0 60 ns eol produc t
data sheet e0068n10 11 (2/2) byte no. function described hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notes 31 module bank density 10h 0 0 0 1 0 0 0 0 64 m bytes 32 command and address signal setup time -a10b 25h 0 0 1 0 0 1 0 1 2.5 ns 33 command and address signal hold time -a10b 10h 0 0 0 1 0 0 0 0 1 ns 34 data signal input setup time -a10b 25h 0 0 1 0 0 1 0 1 2.5 ns 35 data signal input hold time -a10b 10h 0 0 0 1 0 0 0 0 1 ns 36-61 00h 0 0 0 0 0 0 0 0 62 spd revision -a10b 12h 0 0 0 1 0 0 1 0 1.2 63 checksum for bytes 0 C 62 b5h 1 0 1 1 0 1 0 1 64-71 manufactures jedec id code 72 manufacturing location 73-90 manufactures p/n 91-92 revision code 93-94 manufacturing date 95-98 assembly serial number 99-125 mfg specific 126 intel specification frequency -a10b 66h 0 1 1 0 0 1 1 0 66 mhz 127 intel specification /cas latency support -a10b 06h 0 0 0 0 0 1 1 0 timing chart refer to the pd45128441, 45128841, 45128163 data sheet (e0031n) . eol produc t
data sheet e0068n10 12 package drawing 144 pin dual in-line module (socket type) m144s-80a10 item millimeters a b c d e f h i 67.6 29.0 3.7 0.8(t.p.) 23.2 l 25.4 0.15 20.0 3.3 m 3.8 max. 4.6 32.8 n d1 1.5 0.10 d2 4.0 q r2.0 r 4.0 0.10 s 1.8 t 1.0 0.1 u1 3.2 min. u2 4.0 min. v 0.25 max. w 0.6 0.05 y 2.0 min. m1 3.4 m2 22.0 a1 67.6 0.15 h a s (optional holes) a1 (area a) c b e n a (area b) detail of a part y r m1 (area b) l m2 (area a) i f q u2 t u1 m x d2 w d1 v d eol produc t
data sheet e0068n10 13 [memo] eol produc t
data sheet e0068n10 14 [memo] eol produc t
data sheet e0068n10 15 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. eol produc t
caution for handling memory modules when handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ic, chip capacitors and chip resistors. it is necessary to avoid undue mechanical stress on these components to prevent damaging them. when re-packing memory modules, be sure the modules are not touching each other. modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. m8e 00. 4 the information in this document is current as of january, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of elpida's data sheets or data books, etc., for the most up-to-date specifications of elpida semiconductor products. not all products and/or types are available in every country. please check with an elpida memory, inc. for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of elpida. elpida assumes no responsibility for any errors that may appear in this document. elpida does not assume any liability for infringement of patents, copyrights or other intellectual pr operty rights of third parties by or arising from the use of elpida semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual pr operty rights of elpida or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. elpida assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while elpida endeavours to enhance the quality, reliability and safety of elpida semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in elpida semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. elpida semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": tr ansportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of elpida semiconductor products is "standard" unless otherwise expressly specified in elpida's data sheets or data books, etc. if customers wish to use elpida semiconductor products in applications not intended by elpida, they must contact an elpida memory, inc. in advance to determine elpida's willingness to support a given application. (note) (1) "elpida" as used in this statement means elpida memory, inc. and also includes its majority-owned subsidiaries. (2) "elpida semiconductor products" means any semiconductor product developed or manufactured by or for elpida (as defined above). ? ? ? ? ? ? eol produc t

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